Electrical Characterization of sub-30nm Gatelength SOI MOSFETs

Demonstrations of sub 20nm gate length MOSFET devices involving various FEOL (front end of line) schemes such as Silicon On DEpletion Layer (SODEL) FET’s, asymmetricgate FinFET devices, planar Ultra-thin body SOI (UTSOI) FET’s, and, more recently, independently oriented surface channels for (110) pMOS and (100) nMOS described as Simplified Hybrid Orientation Technology (SHOT).[1-4, 718] have been reported. SHOT FEOL integration for FinFETs can be combined on the same wafer as planar PDSOI and UTSOI MOSFETs [18]. According to International Technology Roadmap for Semiconductors (ITRS) guidelines [5] 20nm silicon layers with +/-5%, 6 uniformity will be needed in 2004 timeframe[8] to guarantee threshold voltage ( Vt ) control [6]. Bonded Silicon on Insulator (SOI) processes that achieve +/10 A film thickness have been shown [6] for these Ultra-Thin SOI (UT-SOI) devices at the 65nm node and beyond. UTSOI devices combined with SHOT (110) pMOS and (100) nMOS oriented surface channels offer optimizeed channel carrier mobility as well meeting issues of threshold voltage levels[4-18]. Discrete electrical characterization of sub 30nm gatelength thickness SOI MOSFET devices incorporating 20nm silicon layer thickness and less present challenges to conventional methods of electrical physical contact probing. Besides involving feature sizes below optical light resolution limits, discrete devices at this technology node incorporate an effective-oxide-thickness (EOT) of less than 1.5nm. and gate lengths less than 30nm[1-4, 7, 15-17]. Shrinking critical dimensions (CD) mean SRAM cell sizes of less than 0.75um Additionally, the 20nm silicon layer thickness and the thinning SOI box thickness of 80nm – 150nm [1-4, 15-17 ] in UT-SOI devices may be more sensitive to charging effects from incident energetic SEM electron-beams or Focused Ion Beam (FIB) gallium beams. Atomic Force Probe (AFP) techniques are therefore particularly suited for electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k back end of line (BEOL) interlevel dielectric films. AFP electrical measurements of sub-30nm gatelength SOI MOSFET devices will be described. .